Phase locked loop and associated method for loop gain calibration

ABSTRACT

A phase locked loop (PLL) includes a controllable oscillator, a charge pump, a type II loop filter, a frequency divider, a phase error processing circuit, a phase frequency detector and a phase alignment circuit. The controllable oscillator generates an oscillating signal. The charge pump circuit generates a charge pump output in a calibration mode. The type II loop filter generates a first control signal to the controllable oscillator according to the charge pump output. The frequency divider performs frequency division upon the oscillating signal for generating a feedback signal. The phase error processing circuit outputs an adjusting signal by comparing a reference signal with the feedback signal. The phase frequency detector generates a detection signal by comparing the feedback signal and the reference signal. The phase alignment circuit generates a second control signal in the calibration mode.

CROSS REFERENCE TO RELATED APPLICATION

This application is a division application and claims the benefit ofU.S. Non-provisional application Ser. No. 14/919,708, which was filed onOct. 21, 2015, and is included herein by reference. The U.S.Non-provisional application Ser. No. 14/919,708 claims the benefit ofU.S. Provisional Application No. 62/079,997, which was filed on Nov. 14,2014, and is included herein by reference.

BACKGROUND

The present invention relates to a phase-locked loop (PLL), and moreparticularly, to a loop gain compensation scheme for a controllableoscillator in a PLL, and a method thereof.

FIG. 1 is a related art phase locked loop (PLL) 100. The PLL 100includes a phase/frequency detector 111, a charge pump circuit 112, aloop filter 113, a voltage-controlled oscillator (VCO) 114, a frequencydivider 115 and a modulating device 12. The PFD 111 is arranged toreceive a reference signal F_(ref) and a feedback signal F_(fb), andoutput a pulse signal according to a comparison result of the feedbacksignal F_(fb) and the reference signal F_(ref). The charge pump circuit112 is arranged to convert the pulse signal into an error current. Theloop filter 113 is arranged to integrate the error current to generate acontrol voltage. The VCO 114 is arranged to receive the control voltagefrom the loop filter 113 and generate an oscillating signal F_(VCO)according to the control voltage. The frequency divider 115 is arrangedto generate the feedback signal F_(fb) according to the oscillatingsignal received from the VCO 114.

For simplicity in loop gain calibration, a type I PLL based transmitteris usually applied in communication systems, e.g. the loop filter 113shown in FIG. 1 is a type I PLL. The type I PLL cannot track thetemperature ramping, however, thus causing frequency errors when thetemperature changes.

Therefore, there is a need for a novel method and an associatedapparatus to solve the above issue.

SUMMARY

One of the objectives of the present invention is to provide aphase-locked loop (PLL) with a loop gain calibration scheme to solve theabove issue.

According to an embodiment of the present invention, a PLL is provided.The PLL includes a controllable oscillator, a charge pump, a type IIloop filter, a frequency divider, a phase error processing circuit, aphase frequency detector and a phase alignment circuit. The controllableoscillator is arranged to generate an oscillating signal. The chargepump circuit is arranged to receive a calibration signal and generate acharge pump output according to the calibration signal when the PLLoperates in a calibration mode. The type II loop filter is arranged toreceive the charge pump output, and generate a first control signal tothe controllable oscillator according to the charge pump output. Thefrequency divider is arranged to receive the oscillating signaloutputted from the controllable oscillator and an adjusting signal, andrefer to the adjusting signal to perform frequency division upon theoscillating signal for generating a feedback signal. The phase errorprocessing circuit is arranged to receive the feedback signal and areference signal, and output the adjusting signal based on a comparisonresult of the reference signal and the feedback signal. The phasefrequency detector is arranged to receive the feedback signal and thereference signal, and compare the feedback signal and the referencesignal to generate a detection signal. The phase alignment circuit isarranged to receive the detection signal, and generate a second controlsignal to the controllable oscillator according to the detection signalwhen the PLL operates in the calibration mode.

According to another embodiment of the present invention, a method forcontrolling a PLL is provided. The method includes: configuring acontrollable oscillator (VCO) to generate an oscillating signal (FVCO);generating a charge pump output of a charge pump circuit according to acalibration signal when the PLL operates in a calibration mode;configuring a type II loop filter to receive the charge pump output, andgenerate a first control signal to the controllable oscillator accordingto the charge pump output; referring to an adjusting signal to performfrequency division upon the oscillating signal for generating a feedbacksignal (FDIV); modifying the adjusting signal based on a comparisonresult of a reference signal and the feedback signal; comparing thefeedback signal and the reference signal to generate a detection signal;and generating a second control signal to the controllable oscillatoraccording to the detection signal when the PLL operates in thecalibration mode.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a related art phase locked loop (PLL).

FIG. 2 is a diagram illustrating a PLL according to an embodiment of thepresent invention.

FIG. 3 is a diagram illustrating a phase error processing circuit 300 inthe PLL shown in FIG. 2 according to an embodiment of the presentinvention.

FIG. 4 is a diagram illustrating a PLL according to an embodiment of thepresent invention

FIG. 5 is a diagram illustrating a PLL according to an embodiment of thepresent invention.

FIG. 6 is a flowchart illustrating a detecting method according to anembodiment of the present invention.

DETAILED DESCRIPTION

Certain terms are used throughout the description and following claimsto refer to particular components. As one skilled in the art willappreciate, manufacturers may refer to a component by different names.This document does not intend to distinguish between components thatdiffer in name but not function. In the following description and in theclaims, the terms “include” and “comprise” are used in an open-endedfashion, and thus should not be interpreted as a close-ended term suchas “consist of”. Also, the term “couple” is intended to mean either anindirect or direct electrical connection. Accordingly, if one device iscoupled to another device, that connection may be through a directelectrical connection, or through an indirect electrical connection viaother devices and connections.

FIG. 2 is a diagram illustrating a PLL 200 according to an embodiment ofthe present invention. The PLL 200 includes a controllable oscillator210, a charge pump circuit 220, a type II loop filter 240, a frequencydivider 250, a phase error processing circuit 260 and a phase frequencydetector 280. The controllable oscillator 210 is arranged to generate anoscillating signal FVCO. In this embodiment, the controllable oscillator210 is assumed as a voltage control oscillator (VCO), but the presentinvention is not limited thereto. Note that the PLL 200 may operate inone of a normal operation mode and a calibration mode. When the PLL 200operates in the calibration mode, the charge pump circuit 220 isarranged to receive a calibration signal CAL_Pulse from the phasefrequency detector 280, and generate a charge pump output CP_OUTaccording to the calibration signal CAL_Pulse to the controllableoscillator 210. Further, the phase PFD 280 is arranged to receive thefeedback signal FDIV and the reference signal FREF, and compare thefeedback signal FDIV and the reference signal FREF to generate adetection signal UP/DN.

The type II loop filter 240 is arranged to receive the charge pumpoutput CP_OUT, and generate a control signal CON_1 to the controllableoscillator according to the charge pump output CP_OUT. The frequencydivider 250 is arranged to receive the oscillating signal FVCO outputtedfrom the controllable oscillator 210 and an adjusting signal ΔN from thephase error processing circuit 260, and refer to the adjusting signal ΔNto perform frequency division upon the oscillating signal FVCO forgenerating a feedback signal FDIV. The phase error processing circuit260 is arranged to receive the feedback signal FDIV and a referencesignal FREF in order to generate the adjusting signal ΔN.

The type II loop filter 240 may be composed of passive elements, butthis is not a limitation of the present invention. In some embodiments,the type II loop filter 240 may comprise active elements. In general, atype II loop filter comprises at least a capacitor and a resistorcoupled in series. For example, the loop filter 240 comprises at leastthe capacitor C2 and the resistor R2 coupled in series. During thecalibration, the resistors R2 and R3 may both be short-circuited, inorder to eliminate ripples.

FIG. 3 is a diagram illustrating a phase error processing circuit 300 inthe PLL 200 shown in FIG. 2 according to an embodiment of the presentinvention. The phase error processing circuit 300 may be an embodimentof the phase error processing circuit 260 shown in FIG. 2. The phaseerror processing circuit 300 includes a phase frequency detector (PFD)310, an Up-Down convertor 320 and a sigma-delta modulator (SDM) 340. Byway of example, not limitation, the PFD 310 may be a Bang Bang PFD. ThePFD 310 is arranged to receive the feedback signal FDIV and thereference signal FREF, and compare the feedback signal FDIV and thereference signal FREF to generate a detection signal (denoted aslead/lag in FIG. 3). The detection signal is arranged to inform theUp-Down convertor 320 of the lead/lag information of the comparisonresult of the reference signal FREF and the feedback signal FDIV. Block330 represents that the Up-Down convertor 320 transmits a divisor codesignal N_guess to the SDM 340, wherein the divisor code signal N_guessis generated according to the detection signal. The SDM 340 is arrangedto receive the divisor code signal N_guess and generate the adjustingsignal ΔN based on the divisor code signal N_guess. Specifically, theadjusting signal ΔN is arranged to adjust a dividing factor (e.g. thedivisor number) of the frequency divider 250.

To be more specific, the variation of the dividing factor of thefrequency divider 250 can be represented by Equation 3.1:

$\begin{matrix}{{\Delta \; N} = {\frac{\Delta \; f_{VCO}}{FREF} = {I_{CP}\frac{\Delta \; t}{A_{0}}K_{{VCO}\frac{1}{FREF}}}}} & (3.1)\end{matrix}$

wherein ΔN denotes the variation of the dividing factor applied to thefrequency divider 250, I_(CP) denotes a current value of the charge pumpcircuit 230, Δf_(VCO) denotes a frequency shift of the controllableoscillator 210, Δt denotes a period of the calibration signal CAL_Pulse,and A₀ denotes a capacitance value of the loop filter 240 when the PLL200 operates in the calibration mode. For example, A₀ may represent thecapacitance total of the loop filter 240. In the case of FIG. 2,A₀=C₁+C₂+C₃. Further, the divisor code signal N_guess may be ΔN·2²³ fora 23-bit SDM, but this is not a limitation of the present invention.

The loop gain calibration parameter K_(LG) can be represented byEquation 3.2:

$\begin{matrix}{K_{LG} = {\frac{K_{VCO} \cdot I_{CP}}{N \cdot A_{0}} \cdot \frac{N^{\prime}}{K_{{VCO}^{\prime}} \cdot {I_{{CP}^{\prime}}/A_{0^{\prime}}}}}} & (3.2)\end{matrix}$

wherein K_(VCO) denotes an ideal gain of the controllable oscillator,K_(VCO)′ denotes an actual gain of the controllable oscillator 210 (notethat in following descriptions, each parameter followed by an apostrophe(i.e. prime) relates to an actual case), I_(CP) denotes an ideal currentvalue of the charge pump circuit 230, I_(CP)′ denotes an actual currentvalue of the charge pump circuit 230, N denotes an ideal dividingfactor, N′ denotes an actual dividing factor, A₀ denotes an idealcapacitance value of the type II loop filter 240 when the PLL 200operates in the calibration mode, and A₀′ denotes an actual capacitancevalue of the type II loop filter 240 when the PLL 200 operates in thecalibration mode. In Equation 3.2, loop gain calibration parameterK_(LG) represents a ratio between the ideal gain and actual gain of thecontrollable oscillator 210.

By substituting Equation 3.1 into Equation 3.2, the loop gaincalibration parameter K_(LG) can be obtained by Equation 3.3:

$\begin{matrix}{K_{LG} = {{\frac{{K_{VCO} \cdot I_{CP} \cdot \Delta}\; t}{N \cdot A_{0}} \cdot \frac{N^{\prime}}{{K_{{VCO}^{\prime}} \cdot I_{{CP}^{\prime}} \cdot \Delta}\; {t/A_{0^{\prime}}}}} = {\frac{{K_{VCO} \cdot I_{CP} \cdot \Delta}\; t}{N \cdot A_{0}} \cdot \frac{N^{\prime}}{{N\_ GUESS} \cdot \frac{26M}{2^{23}}}}}} & (3.3)\end{matrix}$

wherein the reference signal FREF in this embodiment is assumed as 26MHz, but this is not a limitation of the present invention.

For the up pulse and the down pulse of the calibration signal CAL_Pulse,Equation 3.3 may be modified as Equation 3.4:

$\begin{matrix}{K_{LG} = {\frac{{K_{VCO} \cdot I_{CP} \cdot \Delta}\; t}{N \cdot A_{0}} \cdot \frac{N^{\prime}}{( {N_{{GUESS}\; 1} - {{N\_ GUESS}\; 2}} ) \cdot \frac{26\; M}{2^{23}}}}} & (3.4)\end{matrix}$

where A₀=C₁+C₂+C₃, N_GUESS1 denotes the divisor code signal for the uppulse (e.g. the logic high part) of the calibration signal CAL_Pulse,and N_GUESS2 denotes the divisor code signal for the down pulse (e.g.the logic low part) of the calibration signal CAL_Pulse.

Through the above calculations, the loop gain calibration parameterK_(LG) may be obtained to calibrate the loop gain of the PLL 200. Forexample, the loop gain calibration parameter K_(LG) may show the extentof the loop gain calibration accuracy, in order to obtain a moreaccurate loop gain. The error/influence caused by the change of the VCOfrequency may be mitigated/eliminated.

FIG. 4 is a diagram illustrating a PLL 400 according to an embodiment ofthe present invention. The difference between the PLL 200 and the PLL400 is that the PLL 400 further includes a phase alignment circuit 450and a multiplexer (MUX) 460. An objective of the phase alignment circuit450 is to accelerate the alignment of the reference signal FREF and thefeedback signal FDIV.

The phase alignment circuit 450 receives the detection signal UP/DN, andgenerates a control signal CON2 to the controllable oscillator 210according to the detection signal UP/DN when the PLL 400 operates in acalibration mode.

The phase alignment circuit 450 may include an auxiliary charge pumpcircuit 451, an auxiliary loop filter 452 and an AND gate 453, as shownin FIG. 4. The auxiliary charge pump circuit 451 is arranged to receivethe detection signal UP/DN and generate an auxiliary charge pump outputCP_OUT1 according to the detection signal. The auxiliary loop filter 452is arranged to receive the auxiliary charge pump output CP_OUT1 from theauxiliary charge pump circuit 451, and generate the second controlsignal CON2 to the controllable oscillator 210 according to theauxiliary charge pump output CP_OUT1. More particularly, the auxiliaryloop filter 452 may be a type I loop filter. The impedance of theauxiliary loop filter 452 may be extremely large (e.g. raise theresistance values of the resistors R0 a and R0 b) to more effectivelyaccelerate the alignment of the reference signal FREF and the feedbacksignal FDIV. Further, the resistance value of the auxiliary loop filter452 (particularly the resistance values resistors R0 a and R0 b) may beadjustable in order to fit various design requirements.

The multiplexer 460 has a first input port (denoted as “1”), a secondinput port (denoted as “0”), and an output port coupled to the chargepump circuit 220. The first input port of the multiplexer 460 isarranged to receive the detection signal UP/DN, the second input port ofthe multiplexer 460 is arranged to receive the calibration signalCAL_Pulse, and the output port of the multiplexer 460 is arranged tooutput the detection signal UP/DN to the charge pump circuit 220 whenthe PLL 400 operates in a normal operation mode, and output thecalibration signal CAL_Pulse to the charge pump circuit 220 when the PLL400 operates in the calibration mode.

Specifically, when the PLL 400 operates in the normal operation mode,the phase alignment circuit 450 is disabled; and when the PLL 400operates in the calibration mode, the phase alignment circuit 450 isenabled. For example, when the PLL 400 operates in the normal operationmode, the enabling signal CAL_EN can be set to 0, so that the chargepump circuit 220 only receives the detection signal UP/DN, and the phasealignment circuit 450 is disabled (due to the AND gate 453). When thePLL 400 operates in the calibration mode, the enabling signal CAL_EN canbe set to 1, so that the charge pump circuit 220 receives thecalibration signal CAL_Pulse, and the phase alignment circuit 450 isenabled (due to the AND gate 453).

Note that, in some modifications of this embodiment, the multiplexer 460may be replaced or removed. For example, the multiplexer 460 may bereplaced with another PFD, so that the PFD 280 is arranged to providesignals to one of the charge pump circuit 220 and the phase alignmentcircuit 450, and the other PFD is arranged to provide signals to theother of the charge pump circuit 220 and the phase alignment circuit450.

FIG. 5 is a diagram illustrating a PLL 500 according to an embodiment ofthe present invention. The difference between the PLL 400 and the PLL500 is that the PLL 500 further includes an offset current source 550arranged to calibrate the control signal outputted to the controllableoscillator (e.g. the calibrated control signal CON1′ shown in FIG. 5).This adaptive compensation scheme may further improve the calibrationaccuracy, and can be applied to the PLL 200 shown in FIG. 2. The offsetcurrent source 550 shown in FIG. 5 is merely for illustrative purposes,and not meant to be a limitation of the present invention.

FIG. 6 is a flowchart illustrating a detecting method according to anembodiment of the present invention. If the result is substantially thesame, the steps are not required to be executed in the exact order shownin FIG. 6. The method shown in FIG. 6 may be employed by any of the PLLs200, 400 and 500, and can be briefly summarized as follows.

Step 602: Start;

Step 604: Configure a controllable oscillator of a PLL to generate anoscillating signal;

Step 606: Configure a type II loop filter to receive the charge pumpoutput, and generate a control signal to the controllable oscillatoraccording to the charge pump output;

Step 608: Refer to an adjusting signal to perform frequency divisionupon the oscillating signal for generating a feedback signal;

Step 610: Modify the adjusting signal based on a comparison result of areference signal and the feedback signal.

Step 610: End.

To summarize, the present invention provides a type II PLL to solve theproblem that a type I PLL cannot track temperature ramping, which causesfrequency errors when the temperature changes. The present inventionalso provides a loop gain calibration scheme to solve the influence ofVCO variations, and a phase alignment circuit to accelerate thealignment of the PFD input phase (e.g. the alignment of the referencesignal FREF and the feedback signal FDIV shown in FIGS. 2, 4 and 5).

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A phase locked loop, comprising: a controllableoscillator, arranged to generate an oscillating signal; a charge pumpcircuit, arranged to receive a calibration signal and generate a chargepump output according to the calibration signal when the PLL operates ina calibration mode; a type II loop filter, arranged to receive thecharge pump output, and generate a first control signal to thecontrollable oscillator according to the charge pump output; a frequencydivider, arranged to receive the oscillating signal outputted from thecontrollable oscillator and an adjusting signal, and refer to theadjusting signal to perform frequency division upon the oscillatingsignal for generating a feedback signal; a phase error processingcircuit, arranged to receive the feedback signal and a reference signal,and output the adjusting signal based on a comparison result of thereference signal and the feedback signal; a phase frequency detector,arranged to receive the feedback signal and the reference signal, andcompare the feedback signal and the reference signal to generate adetection signal; and a phase alignment circuit, arranged to receive thedetection signal, and generate a second control signal to thecontrollable oscillator according to the detection signal when the PLLoperates in the calibration mode.
 2. The PLL of claim 1, wherein thephase alignment circuit comprises: an auxiliary charge pump circuit,arranged to receive the detection signal and generate an auxiliarycharge pump output according to the detection signal; and an auxiliaryloop filter, arranged to receive the auxiliary charge pump output andgenerate the second control signal to the controllable oscillatoraccording to the auxiliary charge pump output.
 3. The PLL of claim 2,wherein the auxiliary loop filter is a type I loop filter.
 4. The PLL ofclaim 1, wherein when the PLL operates in a normal operation mode, thephase alignment circuit is disabled.
 5. The PLL of claim 1, furthercomprising: a multiplexer, having a first input port, a second inputport, and an output port, wherein the first input port is arranged toreceive the detection signal, the second input port is arranged toreceive the calibration signal, and the output port is arranged tooutput the detection signal to the charge pump circuit when the PLLoperates in a normal operation mode, and output the calibration signalto the charge pump circuit when the PLL operates in the calibrationmode.
 6. A method for controlling a phase locked loop (PLL), comprising:configuring a controllable oscillator to generate an oscillating signal;generating a charge pump output of a charge pump circuit according to acalibration signal when the PLL operates in a calibration mode;configuring a type II loop filter to receive the charge pump output, andgenerate a first control signal to the controllable oscillator accordingto the charge pump output; referring to an adjusting signal to performfrequency division upon the oscillating signal for generating a feedbacksignal; modifying the adjusting signal based on a comparison result of areference signal and the feedback signal; comparing the feedback signaland the reference signal to generate a detection signal; and generatinga second control signal to the controllable oscillator according to thedetection signal when the PLL operates in the calibration mode.
 7. Themethod of claim 6, wherein the phase alignment circuit comprises: anauxiliary charge pump circuit, arranged to receive the detection signaland generate an auxiliary charge pump output according to the detectionsignal; and an auxiliary loop filter, arranged to receive the auxiliarycharge pump output and generate the second control signal to thecontrollable oscillator according to the auxiliary charge pump output.8. The method of claim 7, wherein the auxiliary loop filter is a type Iloop filter.
 9. The method of claim 6, wherein when the PLL operates ina normal operation mode, the phase alignment circuit is disabled. 10.The method of claim 6, further comprising: a multiplexer, having a firstinput port, a second input port, and an output port, wherein the firstinput port is arranged to receive the detection signal, the second inputport is arranged to receive the calibration signal, and the output portis arranged to output the detection signal to the charge pump circuitwhen the PLL operates in a normal operation mode, and output thecalibration signal to the charge pump circuit when the PLL operates inthe calibration mode.